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๐Ÿ–ฅ๏ธ [Computer Architecture] CPU ๐Ÿ–ฅ๏ธ

๐Ÿ–ฅ๏ธ CPU(Central Processing Unit; ์ค‘์•™์ฒ˜๋ฆฌ์žฅ์น˜)

๐Ÿ–ฅ๏ธ ALU

ALU(Arithmetic Logic Unit; ์‚ฐ์ˆ ๋…ผ๋ฆฌ์—ฐ์‚ฐ์žฅ์น˜)๋ž€ CPU์˜ ๊ณ„์‚ฐ์„ ๋‹ด๋‹นํ•˜๋Š” ์žฅ์น˜์ž…๋‹ˆ๋‹ค.

  • ALU๊ฐ€ ๋ฐ›์•„๋“ค์ด๋Š” ์ •๋ณด
    • ๋ ˆ์ง€์Šคํ„ฐ(Register)์— ์ €์žฅ๋œ Operand
    • ์ œ์–ด์‹ ํ˜ธ(์ˆ˜ํ–‰ํ•  ์—ฐ์‚ฐ์ด ๋ฌด์—‡์ธ์ง€ ์ œ์–ด์žฅ์น˜(Control Unit)๊ฐ€ ์•Œ๋ ค์ฃผ๋Š” ์‹ ํ˜ธ)
  • ALU๊ฐ€ ๋‚ด๋ณด๋‚ด๋Š” ์ •๋ณด
    • ์—ฐ์‚ฐํ•œ ๊ฒฐ๊ด๊ฐ’์„ ๋ ˆ์ง€์Šคํ„ฐ์— ์ผ์‹œ์ ์œผ๋กœ ์ €์žฅ
    • ํ”Œ๋ž˜๊ทธ(Flag)๋ฅผ ํ”Œ๋ž˜๊ทธ ๋ ˆ์ง€์Šคํ„ฐ์— ์ €์žฅ

๐Ÿ–ฅ๏ธ Control Unit

์ œ์–ด์žฅ์น˜(Control Unit)๋ž€ ์ œ์–ด์‹ ํ˜ธ๋ฅผ ๋‚ด๋ณด๋‚ด๊ณ  ๋ช…๋ น์–ด๋ฅผ ํ•ด์„ํ•˜๋Š” ๋ถ€ํ’ˆ์ž…๋‹ˆ๋‹ค.

  • ์ œ์–ด์žฅ์น˜๊ฐ€ ๋ฐ›์•„๋“ค์ด๋Š” ์ •๋ณด
    • Clock ์‹ ํ˜ธ
    • IR(Instruction Register; ๋ช…๋ น์–ด ๋ ˆ์ง€์Šคํ„ฐ)๋กœ๋ถ€ํ„ฐ ํ•ด์„ํ•ด์•ผ ํ•  ๋ช…๋ น์–ด
    • ํ”Œ๋ž˜๊ทธ ๋ ˆ์ง€์Šคํ„ฐ ์† ํ”Œ๋ž˜๊ทธ ๊ฐ’
    • CPU ์™ธ๋ถ€ ์žฅ์น˜์—์„œ ์ œ์–ด ๋ฒ„์Šค(Control Bus)๋กœ ์ „๋‹ฌ๋œ ์ œ์–ด์‹ ํ˜ธ
  • ์ œ์–ด์žฅ์น˜๊ฐ€ ๋‚ด๋ณด๋‚ด๋Š” ์ •๋ณด
    • CPU ๋‚ด๋ถ€ ์žฅ์น˜์— ์ „๋‹ฌํ•˜๋Š” ์ œ์–ด์‹ ํ˜ธ(Ex. ALU, Register)
    • ์ œ์–ด ๋ฒ„์Šค๋กœ ์ „๋‹ฌํ•˜์—ฌ CPU ์™ธ๋ถ€ ์žฅ์น˜์— ์ „๋‹ฌํ•˜๋Š” ์ œ์–ด์‹ ํ˜ธ(Ex. Memory, I/O Device)

๐Ÿ–ฅ๏ธ Register

๋ ˆ์ง€์Šคํ„ฐ(Register)๋ž€ CPU ๋‚ด๋ถ€์˜ ์ž‘์€ ์ž„์‹œ ์ €์žฅ ์žฅ์น˜๋กœ ํ”„๋กœ๊ทธ๋žจ ์† ๋ช…๋ น์–ด์™€ ๋ฐ์ดํ„ฐ๊ฐ€ ์ €์žฅ๋ฉ๋‹ˆ๋‹ค.

CPU ์•ˆ์—๋Š” ๋‹ค์–‘ํ•œ ๋ ˆ์ง€์Šคํ„ฐ๋“ค์ด ์žˆ๊ณ  CPU ์ข…๋ฅ˜๋งˆ๋‹ค ์„œ๋กœ ๋‹ค๋ฅธ ๋ ˆ์ง€์Šคํ„ฐ๋“ค์„ ๊ฐ€์ง€๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. ๋งŽ์€ CPU๋“ค์ด ๊ณตํ†ต์ ์œผ๋กœ ๊ฐ€์ง€๊ณ  ์žˆ๋Š” ๋ ˆ์ง€์Šคํ„ฐ๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์Šต๋‹ˆ๋‹ค.

RegisterStore
PC(Program Counter) | IP(Insturction Pointer)๊ฐ€์ ธ์˜ฌ ๋ช…๋ น์–ด๊ฐ€ ์ €์žฅ๋˜์–ด ์žˆ๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๋ฅผ ์ €์žฅ
MAR(Memory Address Register)PC์— ์ €์žฅ๋œ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๋ฅผ ์ €์žฅ
MBR(Memory Buffer Register) | MDR(Memory Data Register)MAR์— ์ €์žฅ๋œ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ์— ์ €์žฅ๋˜์–ด ์žˆ๋Š” ๋ช…๋ น์–ด ๋˜๋Š” ๋ฐ์ดํ„ฐ๋ฅผ ์ €์žฅ
IR(Instruction Register)MBR์— ์ €์žฅ๋œ ๋ช…๋ น์–ด๋ฅผ ์ €์žฅ
General Purpose RegisterMAR, MBR๊ณผ ๋‹ค๋ฅด๊ฒŒ ๋ฐ์ดํ„ฐ์™€ ์ฃผ์†Œ ์ƒ๊ด€์—†์ด ์ €์žฅ
Flag RegisterALU ์—ฐ์‚ฐ ๊ฒฐ๊ณผ ์ค‘ Flag๋ฅผ ์ €์žฅ
Stack PointerStack Area์— ๋งˆ์ง€๋ง‰์œผ๋กœ ์ €์žฅ๋œ ๊ฐ’์˜ ์ฃผ์†Œ๋ฅผ ์ €์žฅ
Base Registerํ”„๋กœ๊ทธ๋žจ์˜ ์ฒซ Physical Address๋ฅผ ์ €์žฅ
Limit RegisterLogical Address์˜ ์ตœ๋Œ€ ํฌ๊ธฐ๋ฅผ ์ €์žฅ

๐Ÿ–ฅ๏ธ Cache

Cache(์บ์‹œ)์˜ ๋“ฑ์žฅ ์ด์œ ์™€ ๊ธฐ๋ณธ ์ŠคํŽ™์€ ๋‹ค์Œ๊ณผ ๊ฐ™์Šต๋‹ˆ๋‹ค.

  • ์บ์‹œ ๋“ฑ์žฅ ์ด์œ : CPU์˜ ์—ฐ์‚ฐ ์†๋„์™€ ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ ์†๋„ ์ฐจ์ด๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•ด ๋“ฑ์žฅํ•œ SRAM ๊ธฐ๋ฐ˜์˜ ์ €์žฅ ์žฅ์น˜
  • ์บ์‹œ์˜ ์œ„์น˜: CPU(CPU Core โ” L1 Cache โ” L2 Cache) โ” L3 Cache โ” Memory
  • ์บ์‹œ์˜ ์šฉ๋Ÿ‰: Register < L1 Cache < L2 Cache < L3 Cache < Memory
  • ์บ์‹œ์˜ ์†๋„: Register > L1 Cache > L2 Cache > L3 Cache > Memory

์บ์‹œ์˜ ์ด์ ์„ ์ œ๋Œ€๋กœ ํ™œ์šฉํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” Cache Hit Ratio๋ฅผ ๋†’์—ฌํ•˜๋Š”๋ฐ ์ด๋ฅผ ์œ„ํ•ด ์บ์‹œ๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์€ ์ฐธ์กฐ ์ง€์—ญ์„ฑ ์›๋ฆฌ(Locality Of Reference, Principle Of Locality)์— ๋”ฐ๋ผ ๋ฉ”๋ชจ๋ฆฌ๋กœ๋ถ€ํ„ฐ ๊ฐ€์ ธ์˜ฌ ๋ฐ์ดํ„ฐ๋ฅผ ๊ฒฐ์ •ํ•ฉ๋‹ˆ๋‹ค.

  • ์‹œ๊ฐ„ ์ง€์—ญ์„ฑ(Temporal Locality): CPU๋Š” ์ตœ๊ทผ์— ์ ‘๊ทผํ–ˆ๋˜ ๋ฉ”๋ชจ๋ฆฌ ๊ณต๊ฐ„์— ๋‹ค์‹œ ์ ‘๊ทผํ•˜๋ ค๋Š” ๊ฒฝํ–ฅ์ด ์กด์žฌ
  • ๊ณต๊ฐ„ ์ง€์—ญ์„ฑ(Spatial Locality): CPU๋Š” ์ตœ๊ทผ์— ์ ‘๊ทผํ–ˆ๋˜ ๋ฉ”๋ชจ๋ฆฌ ๊ณต๊ฐ„ ๊ทผ์ฒ˜๋ฅผ ์ ‘๊ทผํ•˜๋ ค๋Š” ๊ฒฝํ–ฅ์ด ์กด์žฌ

Cache Hit Ratio: Cache Hit Ratio $=$ Cache Hit $/$ $($Cache Hit + Cache Miss$)$

๐Ÿ–ฅ๏ธ Multi-Core

Multi-Core(Multi-Core Processor)๋ž€ CPU Core๋ฅผ ์—ฌ๋Ÿฌ ๊ฐœ ํฌํ•จํ•˜๊ณ  ์žˆ๋Š” CPU๋ฅผ ๋งํ•ฉ๋‹ˆ๋‹ค.

์ผ๋ฐ˜์ ์œผ๋กœ Core์˜ ๊ฐœ์ˆ˜๊ฐ€ ์ฆ๊ฐ€ํ•˜๋ฉด ์„ฑ๋Šฅ์ด ์ฆ๊ฐ€ํ•˜์ง€๋งŒ ์—ฐ์‚ฐ ์†๋„๊ฐ€ ๋ฐ˜๋“œ์‹œ Core์˜ ๊ฐœ์ˆ˜์— ๋น„๋ก€ํ•ด์„œ ์ฆ๊ฐ€ํ•˜์ง€๋Š” ์•Š์œผ๋ฉฐ ์ž‘์—…๋Ÿ‰์ด ์ ์€ ๊ฒฝ์šฐ Core์˜ ๊ฐœ์ˆ˜๊ฐ€ ์ฆ๊ฐ€ํ•œ๋‹ค๊ณ  ํ•ด์„œ ์„ฑ๋Šฅ์ด ์ข‹์•„์ง€์ง€๋Š” ์•Š์Šต๋‹ˆ๋‹ค.

๐Ÿ–ฅ๏ธ Multi-Thread

Multi-Thread Processor(Multi-Thread CPU)๋ž€ ํ•˜๋‚˜์˜ Core๋กœ ์—ฌ๋Ÿฌ ๋ช…๋ น์–ด๋ฅผ ๋™์‹œ์— ์ฒ˜๋ฆฌํ•˜๋Š” CPU๋ฅผ ๋งํ•ฉ๋‹ˆ๋‹ค.

ํ•˜๋‚˜์˜ Core๋กœ ์—ฌ๋Ÿฌ ๋ช…๋ น์–ด๋ฅผ ์ฒ˜๋ฆฌํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ํ•˜๋‚˜์˜ ๋ช…๋ น์–ด๋ฅผ ์ฒ˜๋ฆฌํ•˜๋Š”๋ฐ ํ•„์š”ํ•œ ๋ ˆ์ง€์Šคํ„ฐ๊ฐ€ ์—ฌ๋Ÿฌ ๊ฐœ ์žˆ์œผ๋ฉด ๋˜๊ธฐ ๋•Œ๋ฌธ์— Multi-Thread Processor์—์„œ๋Š” ๋ ˆ์ง€์Šคํ„ฐ๊ฐ€ ํ•ต์‹ฌ ์žฅ์น˜์ž…๋‹ˆ๋‹ค.

  • ํ•˜๋“œ์›จ์–ด์  Thread(Logical Processor): ํ•˜๋‚˜์˜ Core๊ฐ€ ๋™์‹œ์— ์ฒ˜๋ฆฌํ•˜๋Š” ๋ช…๋ น์–ด ๋‹จ์œ„
  • ์†Œํ”„ํŠธ์›จ์–ด์  Thread: ํ•˜๋‚˜์˜ ํ”„๋กœ๊ทธ๋žจ์—์„œ ๋…๋ฆฝ์ ์œผ๋กœ ์‹คํ–‰๋˜๋Š” ๋‹จ์œ„
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๐Ÿ–ฅ๏ธ [Computer Architecture] Instruction ๐Ÿ–ฅ๏ธ

๐Ÿ–ฅ๏ธ [Computer Architecture] Memory ๐Ÿ–ฅ๏ธ