Home ๐Ÿ–ฅ๏ธ [Computer Architecture] Memory ๐Ÿ–ฅ๏ธ
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๐Ÿ–ฅ๏ธ [Computer Architecture] Memory ๐Ÿ–ฅ๏ธ

๐Ÿ–ฅ๏ธ ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ VS ๋น„ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ

ย Computer ๋ถ€ํ’ˆExample
Volatile Memory
(ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ)
Register | Cache | Main MemoryRAM, ROM
Non-Volatile Memory
(๋น„ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ)
Secondary StorageHDD, SSD, CD-ROM, USB

ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ์™€ ๋น„ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ์˜ ํŠน์ง• ๋•Œ๋ฌธ์— ์ผ๋ฐ˜์ ์œผ๋กœ ๋น„ํœ˜๋ฐœ์„ฑ์ธ Secondary Storage์—๋Š” ๋ณด๊ด€ํ•  ๋Œ€์ƒ์„ ์ €์žฅํ•˜๊ณ , ํœ˜๋ฐœ์„ฑ์ธ Register, Cache, Main Memory์—๋Š” ์‹คํ–‰ํ•  ๋Œ€์ƒ์„ ์ €์žฅํ•˜์—ฌ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค.

๐Ÿ–ฅ๏ธ RAM

Main Memory์— ์‚ฌ์šฉํ•˜๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ข…๋ฅ˜์—๋Š” ํฌ๊ฒŒ RAM๊ณผ ROM ๋‘ ๊ฐ€์ง€๊ฐ€ ์žˆ์Šต๋‹ˆ๋‹ค. ๊ทธ๋ฆฌ๊ณ  Main Memory๋ผ ํ•จ์€ ๋ณดํ†ต RAM์„ ๋งํ•ฉ๋‹ˆ๋‹ค.

์•ž์„œ ๋งํ–ˆ๋“ฏ์ด Main Memory์—๋Š” ์‹คํ–‰ํ•  ๋Œ€์ƒ์„ ์ €์žฅํ•˜๊ธฐ ๋•Œ๋ฌธ์— RAM์˜ ์šฉ๋Ÿ‰์ด ์ปค์ง€๋ฉด ๋งŽ์€ ํ”„๋กœ๊ทธ๋žจ๋“ค์„ ๋™์‹œ์— ๋น ๋ฅด๊ฒŒ ์‹คํ–‰ํ•˜๋Š”๋ฐ ์œ ๋ฆฌํ•˜๋ฉฐ ๋ฐ˜๋Œ€๋กœ ์šฉ๋Ÿ‰์ด ์ž‘์œผ๋ฉด ๋ณด๊ด€ํ•  ๋Œ€์ƒ์„ ์ €์žฅํ•˜๊ณ  ์žˆ๋Š” Secondary Storage์— ์ ‘๊ทผํ•˜๋Š” ์ผ์ด ๋งŽ์•„์ง€๊ธฐ ๋•Œ๋ฌธ์— ์‹คํ–‰ ์‹œ๊ฐ„์ด ๊ธธ์–ด์ง‘๋‹ˆ๋‹ค.

๐Ÿ–ฅ๏ธ RAM์˜ ์ข…๋ฅ˜

RAM์—๋Š” ํฌ๊ฒŒ DRAM(Dynamic RAM)๊ณผ SRAM(Static Dynamic RAM)์ด ์žˆ์Šต๋‹ˆ๋‹ค.

ย DRAMSRAM
๋ฐ์ดํ„ฐ ์žฌํ™œ์„ฑํ™”ํ•„์š”ํ•จํ•„์š”ํ•˜์ง€ ์•Š์Œ
์†๋„๋Š๋ฆผ๋น ๋ฆ„
๊ฐ€๊ฒฉ์ €๋ ดํ•จ๋น„์Œˆ
์ง‘์ ๋„๋†’์Œ๋‚ฎ์Œ
์†Œ๋น„ ์ „๋ ฅ์ ์Œ๋†’์Œ
์‚ฌ์šฉ ์šฉ๋„Main MemoryCache

๐Ÿ–ฅ๏ธ DRAM์˜ ๋ฐœ์ „

DRAM์€ SDRAM(Synchronous Dynamic RAM), DDR SDRAM(Double Data Rate SDRAM)์œผ๋กœ ๋ฐœ์ „ํ–ˆ์Šต๋‹ˆ๋‹ค.

SDRAM์€ Clock ์‹ ํ˜ธ์™€ ๋™๊ธฐํ™”๋œ ๋ฐœ์ „๋œ ํ˜•ํƒœ์˜ DRAM์ž…๋‹ˆ๋‹ค. ์ดํ›„ DDR SDRAM์ด ๋‚˜์˜ค๋ฉด์„œ SDR SDRAM(Single Data Rate SDRAM)์ด๋ผ ๋ถ€๋ฆ…๋‹ˆ๋‹ค.

DDR SDRAM์€ ๋Œ€์—ญํญ(Data Rate)์ด ๋‘ ๋ฐฐ ๋„“์€ SDRAM์ž…๋‹ˆ๋‹ค. Main Memory๋กœ์„œ DDR SDRAM์„ ๊ฐ€์žฅ ๋งŽ์ด ์‚ฌ์šฉํ•˜๋ฉฐ ์œ„์˜ ๊ทธ๋ฆผ๊ณผ ๊ฐ™์ด ๋Œ€์—ญํญ์˜ ์ˆ˜๋ฅผ $2$๋ฐฐ์”ฉ ๋Š˜๋ ค๊ฐ€๋ฉฐ ๋” ํฐ ๋Œ€์—ญํญ์„ ๊ฐ€์ง€๋Š” DDR SDRAM์„ ์‚ฌ์šฉํ•ฉ๋‹ˆ๋‹ค.

๋Œ€์—ญํญ(Data Rate): ๋ฐ์ดํ„ฐ๋ฅผ ์ฃผ๊ณ  ๋ฐ›๋Š” ๊ธธ์˜ ๋„ˆ๋น„

๐Ÿ–ฅ๏ธ RAM์˜ ์ฃผ์†Œ ๊ณต๊ฐ„

๋ฉ”๋ชจ๋ฆฌ์˜ ์ฃผ์†Œ๋Š” ๋ฌผ๋ฆฌ์ฃผ์†Œ(Physical Address)์™€ ๋…ผ๋ฆฌ์ฃผ์†Œ(Logical Address)๋กœ ๋‚˜๋ˆ„์–ด์ง‘๋‹ˆ๋‹ค.

๋ฌผ๋ฆฌ์ฃผ์†Œ๋Š” ์ •๋ณด๊ฐ€ ์‹ค์ œ๋กœ ์ €์žฅ๋œ H/W์˜ ์ฃผ์†Œ๋ฅผ ์˜๋ฏธํ•˜๊ณ  ๋…ผ๋ฆฌ์ฃผ์†Œ๋Š” CPU(Central Processing Unit; ์ค‘์•™์ฒ˜๋ฆฌ์žฅ์น˜)์™€ ์‹คํ–‰์ค‘์ธ ํ”„๋กœ๊ทธ๋žจ์ด ์‚ฌ์šฉํ•˜๋Š” ์ฃผ์†Œ์ž…๋‹ˆ๋‹ค. ๋˜ํ•œ ๊ฐ ํ”„๋กœ๊ทธ๋žจ์ด ์‹คํ–‰์ค‘์ผ ๋•Œ ๋…ผ๋ฆฌ์ฃผ์†Œ ์‹œ์ž‘์ด $0$๋ฒˆ์ง€์ด๊ธฐ ๋•Œ๋ฌธ์— ๋…ผ๋ฆฌ์ฃผ์†Œ๋ฅผ ํ”„๋กœ๊ทธ๋žจ์˜ ์‹œ์ž‘์ ‘์œผ๋กœ๋ถ€ํ„ฐ ๋–จ์–ด์ง„ ๊ฑฐ๋ฆฌ๋ผ๊ณ  ํ•  ์ˆ˜๋„ ์žˆ์Šต๋‹ˆ๋‹ค.

๐Ÿ–ฅ๏ธ MMU(Memory Management Unit; ๋ฉ”๋ชจ๋ฆฌ ๊ด€๋ฆฌ ์žฅ์น˜)

CPU๊ฐ€ ๋ฌผ๋ฆฌ์ฃผ์†Œ๋ฅผ ์‚ฌ์šฉํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ๋…ผ๋ฆฌ์ฃผ์†Œ๋ฅผ ๋ฌผ๋ฆฌ์ฃผ์†Œ๋กœ ๋ณ€ํ™˜ํ•ด์•ผ ํ•˜๋Š”๋ฐ ์ด ๋•Œ ๊ฐ ํ”„๋กœ๊ทธ๋žจ์ด ์„œ๋กœ์˜ ๋ฌผ๋ฆฌ ์ฃผ์†Œ๋ฅผ ์นจ๋ฒ”ํ•ด์„œ๋Š” ์•ˆ๋ฉ๋‹ˆ๋‹ค. ์ด์ฒ˜๋Ÿผ ๋…ผ๋ฆฌ์ฃผ์†Œ๋ฅผ ๋ฌผ๋ฆฌ์ฃผ์†Œ๋กœ ๋ณ€ํ™˜ํ•ด์ฃผ๋Š” ์žฅ์น˜๋ฅผ MMU๋ผ ํ•ฉ๋‹ˆ๋‹ค.

์ •๋ฆฌํ•˜์ž๋ฉด MMU๋ž€ ๋…ผ๋ฆฌ์ฃผ์†Œ๋ฅผ ๋ฌผ๋ฆฌ์ฃผ์†Œ๋กœ ๋ณ€ํ™˜ํ•˜๋Š” ์žฅ์น˜์ด๋ฉฐ CPU์™€ Address Bus ์‚ฌ์ด์— ์œ„์ฐจํ•œ H/W์ž…๋‹ˆ๋‹ค.

MMU๋Š” Base-Register Addressing Mode๋ฅผ ์‚ฌ์šฉํ•ด ๋…ผ๋ฆฌ์ฃผ์†Œ๋ฅผ ๋ฌผ๋ฆฌ์ฃผ์†Œ๋กœ ๋ณ€๊ฒฝํ•˜๋Š”๋ฐ ๊ฐ ํ”„๋กœ๊ทธ๋žจ์ด ์„œ๋กœ์˜ ๋ฌผ๋ฆฌ์ฃผ์†Œ ์˜์—ญ์„ ์นจ๋ฒ”ํ•˜์ง€ ์•Š๊ธฐ์œ„ํ•ด Limit Register์™€ ๋น„๊ตํ•˜์—ฌ ๋ณ€ํ™˜ํ•ฉ๋‹ˆ๋‹ค.

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๐Ÿ–ฅ๏ธ [Computer Architecture] CPU ๐Ÿ–ฅ๏ธ

๐Ÿ–ฅ๏ธ [Computer Architecture] Secondary Storage ๐Ÿ–ฅ๏ธ